1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor device employing a plug wire connecting an active region included in a transistor and a wire with each other thereby implementing refinement and reducing the resistance of the plug wire.
2. Description of the Prior Art
A semiconductor device is recently so refined, highly integrated and increased in speed that plug wires of low resistance at a small pitch are extremely important. FIG. 43 is a plan view of a conventional semiconductor device in a stage of forming a second layer wire 114, and FIG. 44 is a sectional view taken along the line XLIVxe2x80x94XLIV in FIG. 43. Referring to FIGS. 43 and 44, an element isolation film 102 is provided on a silicon substrate 101 for isolating element regions from each other. A gate electrode 104 is formed on a gate oxide film 103 provided on the silicon substrate 101. A first layer wire 154, provided in parallel with the gate electrode 104 to have the same structure as the gate electrode 104, is arranged on the element isolation film 102.
An extension 106 of an n-conductivity type low-concentration region is arranged to hold a channel region located under the gate oxide film 103 between the same and another extension 106, and an active region (source/drain region) 108 of an n+-conductivity type high-concentration region is formed in continuation to the extension 106. The active region includes both of the aforementioned n+-conductivity type high-concentration region 108 and the extension 106.
Side wall insulator films 107 are formed to cover the side surfaces of the gate electrode 104 and surface parts of the silicon substrate 101 located on the bases thereof, and an interlayer isolation film 109 is formed to cover these elements. The second layer wire 114 is formed on the interlayer isolation film 109. Two contact holes 119 and 131 are opened in the interlayer isolation film 109. A plug wire 129 is embedded in the contact hole 119 for rendering the second layer wire 114 and the first layer wire 154 electrically conductive. Another plug wire 133 is embedded in the other contact hole 131 for rendering the second layer wire 114 and the active region 108 electrically conductive. Barrier metal layers 129a and 133a are provided on the side surfaces and the bottom surfaces of the plug wires 129 and 133 respectively, while a barrier metal layer 114a is provided also on the bottom portion of the second layer wire 114.
As shown in FIGS. 43 and 44, the distance between the plug wire 133 in contact with the active region 108 and the plug wire 129 in contact with the first layer wire 154 cannot be reduced beyond the minimum pitch L in plane. Therefore, the space between a gate electrode 104 provided on an active transistor and the gate electrode 154 provided on the element isolation film 102 is spread to about 1.5 times to twice the minimum pitch L, to disadvantageously increase the plane size (layout) of a memory cell or a peripheral circuit part of a logic circuit of an SRAM (static random access memory), for example.
When the thickness of the interlayer isolation film 109 is increased and the contact holes 119 and 131 are reduced in size, the resistance of wires including the plug wires 129 and 133 coupling the active region 108 and the gate electrode 104 with each other is disadvantageously extremely increased, for example.
Furthermore, a local wire included in the second layer wire 114 on the interlayer isolation film 109, for coupling the plug wire 133 provided on the active region 108 and the plug wire 129 provided on the first layer wire 154 disadvantageously limits the degree of freedom in the layout of the remaining wires.
An object of the present invention is to refine the plane size of a memory cell a peripheral circuit part of a logic circuit of a semiconductor device.
Another object of the present invention is to reduce the electric resistance of a wire including a plug wire and enlarge the degree of freedom in layout of the wire on an interlayer isolation film.
A semiconductor device according to the present invention comprises an active region included in a transistor formed on a semiconductor substrate, a wire formed on the semiconductor substrate, an interlayer isolation film covering the active region and the wire, and a plug wire having a shape overlapping with both of the wire and the active region in plane through the interlayer isolation film, for electrically connecting the wire and the active region with each other.
According to this structure, the electric resistance of the plug wire can be reduced. Furthermore, miniaturization of the plane size of the semiconductor device such as a memory cell of an SRAM generally limited by the space between contact holes can be further advanced. No second layer wire may be required for merely electrically connecting the active region and the aforementioned wire with each other. Therefore, the degree of freedom in the layout of the second layer wire on the interlayer isolation film can be increased. The aforementioned transistor may be any transistor such as a MOSFET (metal-oxide-semiconductor field-effect transistor) so far as the same is a field-effect transistor. For example, the wire according to the present invention may be any wire so far as the same is not a gate electrode in the transistor including the active region.
In the semiconductor device according to the present invention, the wire can be the gate electrode of a transistor located adjacent to the transistor including the active region.
According to this structure, the miniaturization of an SRAM, a multistage amplifier, a wired logic circuit or the like can be promoted. Furthermore, the electric resistance of the plug wire itself can be reduced.
In the semiconductor device according to the present invention, the wire can be located on an element isolation film isolating an element region to which the transistor including the active region belongs from another element region.
According to this structure, electrical connection between the active region and the wire can be implemented with a single plug, for prompting miniaturization of the semiconductor device. Furthermore, no second layer wire may be provided for merely electrically connecting the active region and the wire with each other.
In the semiconductor device according to the present invention, the side surface of the wire can be covered with an insulating layer continuously covering the side surface of the wire and a surface part of the semiconductor substrate located on the base of the side surface in a cross section of the wire.
According to this structure, it is possible to prevent the surface of an extension region from damage when removing a side wall outer-layer spacer from the gate electrode.
In the semiconductor device according to the present invention, the side surface of the wire can be covered with an insulating layer covering only the side surface of the wire in a cross section of the wire.
According to this structure, the contact area between the plug wire and the active region can be increased for reducing the electric resistance on the interface between the plug wire and the active region.
The semiconductor device according to the present invention can further comprise a second active region included in a transistor, different from the transistor including the active region, located adjacent to the wire, while the plug wire can be provided in a shape also overlapping with the second active region in plane in addition to the wire and the active region for electrically connecting the wire and the active region with the second active region.
According to this structure, the area of the cross section of the plug wire is increased and the electric resistance of the plug wire is reduced, while three plugs are integrated into one plug so that remarkable refinement can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.